Efficient Multiplication Carry-Save on-The Fly Correction with Advanced Vedic and Baugh-Wooley Methodologies

The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional multiplier technology. We have designed 16 bit Vedic multiplier using Carry-Save technology and used comparative simulation results that indicate the performance of the circuit. Vedic mathematics is a ancient Indian mathematics is very useful for doing tedious and cumbersome mathematical calculation at a very fast rate. The Vedic multiplier is approximately 10 times faster performance than the conventional multiplier architecture. Experiments show that our proposed multiplier schemes have only shorter delay with respect to a conventional Booth radix-4 multiplier schemes.